The growth of AI and machine learning applications has necessitated the development of high-performance interconnection solutions between large ASICs and linear optical modules. To meet these requirements, TeraSignal has launched TSLink, reportedly the first intelligent Chip-to-Module (C2M) interconnect designed to seamless connect large ASICs and linear optical modules.

Traditional interconnects rely on DSPs to manage data transmission, leading to increased power consumption and latency. By automating link training and performance monitoring, TSLink eliminates the need for DSPs (Digital Signal Processors) in the optical module, dramatically reducing power consumption and latency while simplifying the deployment, enabling a true plug-and-play solution. TSLink leverages the DSP-based SerDes functionality already present in AI ASICs and GPUs, providing a streamlined connection that optimizes performance across various protocols and modulation schemes.

Embedded Intelligence

TSLink eliminates these bottlenecks by embedding intelligence directly into the interconnect, ensuring that data moves seamlessly across the system without the need for redundant digital signal processing. It utilizes advanced Impulse Response Link Training (IRLT) to accurately characterize and compensate for channel impairments, such as Inter-Symbol Interference (ISI), reflection, and crosstalk.

Related:OCP-Compliant Connector Provides One-Stop Solution for Data Centers

By embedding this intelligent link training directly into the interconnect, TSLink ensures high signal integrity with reduced bit error rates, all while minimizing power consumption and eliminating the need for the DSP in the optical module. This protocol-agnostic approach provides flexibility across various high-speed serial protocols, making TSLink an adaptable solution for next-generation AI centric data centers and high-performance computing environments.

“This is essentially a plug-and-play solution that does not require programming,” said Dr. Armond Hairapetian, Founder and CEO of TeraSignal, in an interview with Design News.  

Incorporates CMIS

By leveraging CMIS (Common Management Interface Specification), TSLink automatically characterizes the host to module channel and provides the optimum settings for the DSP-based transmitter in the host.  TSLink includes features like digital eye monitoring and BER reporting, allowing users to easily monitor channel conditions and ensure optimal performance in the link.

The interconnect eliminates the quantization noise introduced by analog-to-digital converters (ADCs) in DSP-based Re-Timers, significantly improving the Bit Error Rate in the link. The advanced link training process shapes the transmit signal based on the characteristics of each individual channel, ensuring maximum signal to noise ratio at the receiver.

Related:Four Trends Defining the Future of Connectivity

Performance Monitoring

Due to the digital nature of TSLink, the analog signal received at the module is sub-sampled and digitized, effectively providing a digital sub-sampling oscilloscope capability inside the module. This capability allows continuous monitoring of the signal and reporting diagnostic metrics such as Signal to Noise Ratio (SNR) and Bit-Error-Rate (BER). These metrics provide the information that are needed for deployment and management of optical interconnects in datacenters.

Removing the DSP results in at least a 50% reduction in silicon die size, contributing to lower production costs and higher density linear optics. The link interfaces Linear Pluggable Optics (LPO), Near Package Optics (NPO), Co-Packaged Optics (CPO) as well as Active Copper Cables (ACC). The interconnect technology is designed to be agnostic to protocols (Ethernet, PCIe, InfiniBand, etc.), modulation schemes (NRZ, PAM4, etc.) and media (Fiber, Copper), thus increasing flexibility across different applications.

TeraSignal is now offering TSLink reference designs, complete with TSLink firmware and the TS8401/02 Intelligent Re-Driver, to select partners and customers. Broader TSLink reference design availability is expected later this year.